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Planar metallization failure modes i...

Zhu, Ning.

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Planar metallization failure modes in integrated power electronics modules.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Planar metallization failure modes in integrated power electronics modules./
作者:	Zhu, Ning.
面頁冊數:	160 p.
附註:	Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1078.
Contained By:	Dissertation Abstracts International67-02B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3207993
ISBN:	9780542557552

Planar metallization failure modes in integrated power electronics modules.
Zhu, Ning.

Planar metallization failure modes in integrated power electronics modules. - 160 p.

Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1078.

Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2006.

Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications.

ISBN: 9780542557552Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Planar metallization failure modes in integrated power electronics modules.
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500 $a Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1078.
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502 $a Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2006.
520 $a Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications.
520 $a However, planar integration technology is a packaging approach with a large contact area between different materials. This may result in unknown failure mechanisms in power applications. Extensive research has already been done to study the performance, processing, and reliability of the planar interconnects in thin film structures. The thickness of the thin films used in integrated circuits (IC) or microelectronics applications ranges from the magnitude of nanometers to that of micrometers. In this work, we are interested in adopting planar interconnections to Integrated Power Electronics Modules (IPEM). In Integrated Power Electronics Modules (IPEMs), copper traces, especially bus traces, need to conduct current ranging from a few amps to tens of amps. One of the major differences between IC and IPEM is that the metal layer in IPEMs (normally >75mum) is much thicker than that of the thin films in IC (normally <1mum). The other major difference, which is also a feature of IPEM, is that the planar metallization is deposited on different brittle substrates. In active IPEM, switching devices are in a bare die form with no encapsulation. The copper deposition is on top of the silicon chips and the insulation polyimide layer. (Abstract shortened by UMI.)
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