東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Massive MIMO detection algorithm and...

Liu, Leibo.

FindBook

Google Book

Amazon

博客來

Massive MIMO detection algorithm and VLSI architecture

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Massive MIMO detection algorithm and VLSI architecture/ by Leibo Liu, Guiqiang Peng, Shaojun Wei.
作者:	Liu, Leibo.
其他作者:	Peng, Guiqiang.
出版者:	Singapore :Springer Singapore : : 2019.,
面頁冊數:	xvi, 336 p. :ill., digital ;24 cm.
內容註:	Chapter 1 Introduction -- Chapter 2 Linear Massive MIMO Detection Algorithm -- Chapter 3 Architecture of Linear Massive MIMO Detection -- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm -- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection -- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection -- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
Contained By:	Springer eBooks
標題:	MIMO systems. -
電子資源:	https://doi.org/10.1007/978-981-13-6362-7
ISBN:	9789811363627

Massive MIMO detection algorithm and VLSI architecture
Liu, Leibo.

Massive MIMO detection algorithm and VLSI architecture[electronic resource] /by Leibo Liu, Guiqiang Peng, Shaojun Wei. - Singapore :Springer Singapore :2019. - xvi, 336 p. :ill., digital ;24 cm.

Chapter 1 Introduction -- Chapter 2 Linear Massive MIMO Detection Algorithm -- Chapter 3 Architecture of Linear Massive MIMO Detection -- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm -- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection -- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection -- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

ISBN: 9789811363627

Standard No.: 10.1007/978-981-13-6362-7doiSubjects--Topical Terms:

811587
MIMO systems.

LC Class. No.: TK5103.4836

Dewey Class. No.: 621.384

Massive MIMO detection algorithm and VLSI architecture
LDR:02517nmm a2200325 a 4500 001 2179760
003 DE-He213
005 20190220151420.0
006 m d
007 cr nn 008maaau
008 191122s2019 si s 0 eng d
020 $a 9789811363627 $q (electronic bk.)
020 $a 9789811363610 $q (paper)
024 7 $a 10.1007/978-981-13-6362-7 $2 doi
035 $a 978-981-13-6362-7
040 $a GP $c GP
041 0 $a eng
050 4 $a TK5103.4836
072 7 $a UK $2 bicssc
072 7 $a COM067000 $2 bisacsh
072 7 $a UK $2 thema
082 0 4 $a 621.384 $2 23
090 $a TK5103.4836 $b .L783 2019
100 1 $a Liu, Leibo. $3 3332215
245 1 0 $a Massive MIMO detection algorithm and VLSI architecture $h [electronic resource] / $c by Leibo Liu, Guiqiang Peng, Shaojun Wei.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2019.
300 $a xvi, 336 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1 Introduction -- Chapter 2 Linear Massive MIMO Detection Algorithm -- Chapter 3 Architecture of Linear Massive MIMO Detection -- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm -- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection -- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection -- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
520 $a This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
650 0 $a MIMO systems. $3 811587
650 0 $a Wireless communication systems. $3 567106
650 1 4 $a Computer Hardware. $3 892776
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Computer Engineering. $3 1567821
650 2 4 $a Wireless and Mobile Communication. $3 3338159
650 2 4 $a Information and Communication, Circuits. $3 893882
700 1 $a Peng, Guiqiang. $3 3385180
700 1 $a Wei, Shaojun. $3 3332216
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-981-13-6362-7
950 $a Computer Science (Springer-11645)